Many similarities exist between seemingly unrelated designs in consumer, industrial, and telecommunication electronics. Examples of similarities include intelligent control, general-purpose circuits (e.g., LCD drivers and I/O ports) and application-oriented circuits. One prior art two-wire bus is a bi-directional two-wire, low to medium speed, serial communication bus designed to exploit such similarities in electrical circuits. The two-wire bus was developed in the early 1980s and was created to reduce manufacturing costs of electronic products.
Prior to the two-wire bus, chip-to-chip communications used a large plurality of pins in a parallel interface. Many of these pins were used for chip-to-chip addressing, selection, control, and data transfers. For example, in a parallel interface, eight data bits are typically transferred from a sender integrated circuit (IC) to a receiver IC in a single operation. The two-wire buts performs chip-to-chip communications using two wires in a serial interface, allowing ICs to communicate with fewer pins. The two wires in the bus carry addressing, selection, control, and data, serially, one bit at a time. A data (SDA) wire carries the data, while a clock (SCL) wire synchronizes the sender and receiver during the transfer. ICs utilizing the two-wire bus can perform similar functions to their larger parallel interface counterparts, but with far fewer pins.
Two-wire bus devices are classified as master or slave. A device that initiates a message is called a master (multiple masters are possible), while a device that responds to a message is called a slave (multiple slaves are also possible). A device can potentially be master, slave, or switch between master and slave, depending on a particular device and application. Hence, the device may at one point in time be a master while the device later takes on a role as slave. The two-wire bus can connect a plurality of ICs using two-wires (SDA and SCL, described supra).
Contemporary two-wire slave devices maintain a unique address. Therefore, part of a two-wire protocol requires a slave address at the beginning of a message. (Two-wire protocol specifications are well known. See, for example, U.S. Published Patent Application 2002/0176009 to Johnson et al. entitled “Image Processor Circuits, systems, and Methods.”) Consequently, all devices on the two-wire bus hear the message, but only the slave that recognizes its own address communicates with the master. Devices on the two-wire bus are typically accessed by individual addresses, for example, 00-FF where even addresses are used for writes and odd addresses are used for reads.
Since two-wire buses can connect a number of devices simultaneously to the same pair of bus wires, a problem results when one of the devices malfunctions and pulls a bus signal (clock or data) low; the bus becomes inoperative and a determination of which of the numerous devices connected to the two-wire bus is responsible becomes difficult. A similar problem occurs when one of the bus conductors becomes shorted to a low impedance source, such as, for example, a ground potential.
FIG. 1 is a prior art example of a practical application of a two-wire bus. FIG. 1 includes a digital signal processor (DSP) 115 (here, the DSP 115 functions as a master device). External pins of the DSP 115 are a bidirectional data pin (SDA) and a serial clock (SCL) pin, both of which are coupled to various slave devices 107, 109 on the two-wire bus via a serial data line 103 and a serial clock line 105. Both the serial data line 103 and the serial clock line 105 are connected respectively via a first 111 and second 113 external pullup resistor to a positive supply voltage VDD on a power supply line 101. When the two-wire bus is free, the serial data line 103 is at logic HIGH. Output stages of the slave devices 107, 109 connected to the two-wire bus typically have an open-drain or open-collector in order to perform a wired-OR function. Data on the contemporary prior art two-wire bus is transferred at a rate of up to 400 kbits/sec in fast mode. According to the two-wire specification, the number of interfaces to the bus is dependent, in part, to limiting bus capacitance to 400 picofarads.
In another practical example of an application of a two-wire bus, FIG. 1B, a data portion of a first 120 and a second 130 integrated circuit each connect to a data bus B. In the first integrated circuit 120 a data input A1 connects to the gate input of an KNOS transistor N1. A source node of the NMOS transistor N1 connects to GND. The NMOS transistor N1 has its drain configured as an output OUT1 of the first integrated circuit 120 which connects to the data bus B.
The second integrated circuit 130 is configured identically to the first integrated circuit 120. For instance, a data input A2, an NMOS transistor N2, and an output OUT2 are all arranged and connected as their counterparts are in the first integrated circuit 120. The second integrated circuit 120 is connected to the data bus B at the output OUT2 in a wired-OR configuration. The voltage potential of the data bus B is pulled up to VDD by a pullup resistor RPU when not pulled-down by either of the NMOS transistors N1, N2.
With Reference to FIG. 1C, a rising edge 143 of a positive data pulse 145, applied at the data input A1 of the first integrated circuit 120 (FIG. 1B), triggers the NMOS transistor N1 to conduct and cause a falling edge 147 as the data bus B is pulled to a low logic level. A falling edge 149 of the positive data pulse 145 deactivates the NMOS transistor N1, allowing the pullup resistor RPU to begin a rising ramp 151 of the potential of the data bus B. The rising ramp 151 of the potential of the data bus B progresses at a rate equal to an RC time constant of the network. The data input A2 and the output OUT2 of the second integrated circuit 130 operate on the data bus B analogously to the first integrated circuit 120. In this way a wired-OR type of driver connection between multiple integrated circuits 120, 130 is accomplished.
With reference to FIG. 2, another prior art application of a two-wire bus includes a microcontroller 201 with two of the I/O pins used for clock (“CLK”) and data (“DATA”) signals coupled to a first serial EEPROM memory device 203A and an eighth serial EEPROM memory device 203H. Up to eight serial EEPROM devices may share a two-wire bus 209 under the two-wire protocol (partially described herein), utilizing the same two microcontroller CLK and DATA I/O pins. Each serial EEPROM device must have its own address inputs (A0, A1, and A2) hard-wired to a unique address to be accessible. With continued reference to FIG. 2, the first serial EEPROM device 203A recognizes address zero (“0”) (A0, A1, and A2 are all tied LOW) while the eighth serial EEPROM device 203H recognizes address seven (“7”) (A0, A1, and A2 are all tied HIGH) The serial EEPROM devices 203A . . . 203H are slave devices, receiving or transmitting data received on the two-wire bus 205 in response to orders from a master device; here, the microcontroller 201 is the master device.
The microcontroller 201 initiates a data transfer by generating a start condition on the two-wire bus 205. This start condition is followed by a byte containing the device address of the intended EEPROM device 203A . . . 203H. The device address consists of a four-bit fixed portion and a three-bit programmable portion. The fixed portion must match a value hard-wired into the slave, while the programmable portion allows the microcontroller 201, acting as master, to select between a maximum of eight slaves on the two-wire bus 205. An eighth bit specifies whether a read or write operation will occur.
The two-wire bus 205 is tied to VDD through a clock line weak resistor 207 and a data line weak resistor 209. If no device is pulling the two-wire bus 205 to ground, the bus 205 will be pulled up by the weak resistors 207, 209 indicating a logic “1” (HIGH). If the microcontroller 201 or one of the EEPROM memory device 203A . . . 203H slaves pulls the bus 205 to ground, the bus will indicate a logic “0” (LOW).
However, despite a widespread use of the two-wire bus, the bus suffers from numerous drawbacks. For example, the two-wire bus is noisy, requiring a noise suppression circuit to filter noise when data are present on the bus. The noise suppression circuit reduces EEPROM device I/O speed. Further, when an EEPROM device outputs a logic “1” onto the two-wire bus, the device relies on the weak resistor to pullup the bus. Therefore, a data transfer rate is limited by the strength of the weak resistor 209 due to an increased RC time constant. It a stronger resistor is employed, a stronger pulldown device is required thus consuming more current to output a logic “0” onto the bus.
Therefore, what is needed is a dual-wire bus that is usable with contemporary communication specifications and protocols that produces less noise and is capable of higher data transfer rates.